Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. Nos. 6,747,310 and 7,927,994 disclose a split gate non-volatile memory (NVM) cell, which are incorporated herein by reference for all purposes. FIG. 1 illustrates an example of such conventional split gate memory cells 10 formed on a semiconductor substrate 12. Source and drain regions 14 and 16 are formed as diffusion regions in silicon substrate 12, and define a channel region 18 therebetween. Each memory cell 10 includes four conductive gates: a floating gate 20 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 14, a control gate 22 disposed over and insulated from the floating gate 20 by insulation layer 23, an erase gate 24 disposed over and insulated from the source region 14, and a select gate 26 (commonly referred to as the word line gate) disposed over and insulated from a second portion of the channel region 18. A conductive contact 28 electrically connects the drain region 16 to a conductive bit line 30, that electrically connects to all the drain regions in the column of memory cells 10. The memory cells 10 are formed in pairs that share a common source region 14 and erase gate 24. Adjacent pairs of memory cells share a common drain region 16 and conductive contact 28. Typically, the memory cell pairs are formed in an array of rows and columns of the memory cells 10.
Memory cells 10 are programmed by injecting electrons onto the floating gate 20. The negatively charged floating gate 20 causes a reduced or zero conductivity in the underlying channel region 18, which is read as a “0” state. Memory cells 10 are erased by removing the electrons from the floating gate 20, which allows the underlying channel region to conduct when the corresponding select gate 26 and control gate 22 are raised to their reading voltage potentials. This is read as a “1” state. Memory cells 10 can be repeatedly programmed, erased and re-programmed.
There are applications where read only memory (ROM) is formed on the same chip as the NVM array. ROM includes memory cells that are only programmable once, and thereafter cannot be erased or re-programmed. ROM is formed on the same chip as the NVM array to provide code that cannot be changed. For many such applications, the code needs to be secure (i.e. once programmed, the user or hacker should not be able to change it or hack it). The NVM cells are not appropriate for storing this secure code, because the user could accidentally program code over this secure code, or it could be hacked by those with malicious intentions. One solution has been to provide a dedicated ROM structure that is separate from, but on the same chip as, the NVM array. However, such a dedicated structure is easily identifiable and therefore subject to the same hacking threat. Moreover, forming dedicated ROM structures requires separate processing and masking steps relative to the NVM array, which can drive up the complexity and the cost of manufacturing the chip.
There is a need for implementing ROM on the same chip as NVM which is secure and which does not require excessive processing to fabricate.